1. Field of the Invention
The present invention relates generally to a silicon wafer and a method for producing the same. Although not limited, the present invention relates more specifically to a silicon wafer which is formed through a Czochralski method (hereinafter referred also to as CZ method) and is suitably used as a substrate for an insulated gate bipolar transistor (hereinafter referred also to as IGBT), and to a method for producing the silicon wafer.
2. Description of the Related Art
An insulated gate bipolar transistor (IGBT) has a structure including a MOSFET provided with a PN junction for hole injection. In the structure, a gate and an emitter are formed on a front surface side of an n− type silicon layer with high resistivity, and a collector is formed on the back surface side thereof over the PN junction.
The IGBT is a device in which an electric current between the collector and the emitter is controlled by an electric voltage applied to the gate being provided on a silicon oxide film. Due to the hole injection from the collector to the n− type silicon layer positioned between the gate and the emitter side and the collector side, the IGBT has features that an on-resistance may be reduced and that it is not easily destroyed even if a high electric current flows therethrough.
The IGBT controls an electric current by the gate provided on the oxide film, as described above, it is accordingly desirable for the gate oxide film to be free from defects. In addition, since the electric current flows between the emitter on the front surface of the device and the collector on the back surface, defects in a wafer have a large influence on the properties of the IGBT. Therefore, in the prior art, an epitaxial layer of an epitaxial wafer or a silicon wafer formed through a FZ method has been used as a substrate for the IGBT.
However, an n type silicon layer for providing an IGBT with high breakdown voltage is required to have a thickness of approximately 150 μm. In order to realize such a thickness by means of the epitaxial layer, a long time is required for an epitaxial growth process, and therefore the problem is that a significant increase in production cost cannot be avoided.
On the other hand, in the case of forming a silicon wafer through the FZ method, the amount of impurities contaminated during a production process is small, and therefore it is possible to obtain a wafer with relatively less defects compared to the case through the CZ method. However, the problems are that it is difficult to obtain a wafer having large diameter through the FZ method and that the FZ method is not appropriate for mass production.
Meanwhile, silicon wafers formed through the CZ method include defects caused from microscopic voids of 0.1 to 0.3 μm in size. If such defects are exposed to the surface of a wafer, the defects form pits on the wafer surface. These defects are generally called as COP (Crystal Originated Particle). It has been impossible to use a wafer having COPs as it stands as a substrate for an IGBT.
Considering the above, as described in Patent Documents 1 and 2, methods for producing a wafer has been developed, in which the number of COPs is reduced by performing a heat treatment on a wafer obtained through the CZ method.    Patent Document 1: International Publication WO2004/073057 pamphlet    Patent Document 2: Japanese Unexamined Patent Publication No. 2006-344823